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| (R) HA-5102, HA-5104 Data Sheet June 2003 FN2925.8 Dual and Quad, 8MHz and 60MHz, Low Noise Operational Amplifiers Low noise and high performance are key words describing HA-5102 and HA-5104. These general purpose amplifiers offer an array of dynamic specifications including a 3V/s slew rate and 8MHz bandwidth. Complementing these outstanding parameters is a very low noise specification of 4.3nV/Hz at 1kHz. Fabricated using the Intersil high frequency DI process, these operational amplifiers also offer excellent input specifications such as a 0.5mV offset voltage and 30nA offset current. Complementing these specifications are 108dB open loop gain and 60dB channel separation. Consuming a very modest amount of power (90mW/ package for duals and 150mW/package for quads), HA-5102/04 also provide 15mA of output current. This impressive combination of features make this series of amplifiers ideally suited for designs ranging from audio amplifiers and active filters to the most demanding signal conditioning and instrumentation circuits. These operational amplifiers are available in dual or quad form with industry standard pinouts allowing for immediate interchangeability with most other dual and quad operational amplifiers. HA-5102 Dual, Comp. HA-5104 Quad, Comp. Refer to the /883 data sheet for military product. Features * * * * * Low Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3nV/Hz Bandwidth . . . . . . . . . . . . . . . . . . . 8MHz (Compensated) Slew Rate. . . . . . . . . . . . . . . . . . . . 3V/s (Compensated) Low Offset Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 0.5mV Available in Duals or Quads Applications * * * * * * High Q, Active Filters Audio Amplifiers Instrumentation Amplifiers Integrators Signal Generators For Further Design Ideas, See Application Note AN554 Pinouts HA-5102 (CERDIP) TOP VIEW OUT1 1 -IN1 2 +IN1 3 V- 4 + + 8 V+ 7 OUT2 6 -IN2 5 +IN2 HA-5104 (CERDIP) TOP VIEW OUT1 1 14 OUT4 1 + 4 + 13 -IN4 12 +IN4 11 V+ Ordering Information TEMP. RANGE PART NUMBER (oC) HA7-5102-2 HA1-5104-2 HA1-5104-5 HA9P5104-9 -55 to 125 -55 to 125 0 to 75 -40 to 85 PACKAGE 8 Ld CERDIP 14 Ld CERDIP 14 Ld CERDIP 16 Ld SOIC PKG. DWG. # F8.3A F14.3 F14.3 M16.3 -IN1 2 +IN1 3 V+ 4 +IN2 5 -IN2 6 OUT2 7 - + 10 +IN3 9 -IN3 8 OUT3 - 2 3 HA5104 (SOIC) TOP VIEW OUT1 1 -IN1 2 +IN1 3 V+ 4 +IN2 5 -IN2 6 OUT2 7 NC 8 + 16 OUT4 1 + 4 + 15 -IN4 14 +IN4 13 V+ 12 +IN3 11 -IN3 10 OUT3 9 NC - 2 3 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HA-5102, HA-5104 Absolute Maximum Ratings Supply Voltage Between V+ and V- Terminals . . . . . . . . . . . . . 40V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Output Short Circuit Duration (Note 3). . . . . . . . . . . . . . . . Indefinite Thermal Information Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W) 8 Lead CERDIP Package. . . . . . . . . . . 115 28 14 Lead CERDIP Package. . . . . . . . . . 75 20 SOIC Package . . . . . . . . . . . . . . . . . . . 100 N/A Maximum Junction Temperature (Note 1, Hermetic Package) . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range HA-5102/5104-2 . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HA-5104-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC HA-5104-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation, including output load, must be designed to maintain the maximum junction temperature below 175oC for hermetic packages, and below 150oC for plastic packages. 2. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 3. Any one amplifier may be shorted to ground indefinitely. Electrical Specifications VSUPPLY = 15V, Unless Otherwise Specified TEMP. (oC) HA-5102-2 MIN TYP MAX HA-5104-2, -5 MIN TYP MAX MIN HA-5104-9 TYP MAX UNITS PARAMETER INPUT CHARACTERISTICS Offset Voltage 25 Full 12 0.5 3 130 30 500 - 2.0 2.5 200 325 75 125 - 12 0.5 3 130 30 500 - 2.5 3.0 200 325 75 125 - 12 0.5 3 130 30 500 - 2.5 3.0 200 500 75 125 - mV mV V/oC nA nA nA nA k V Offset Voltage Average Drift Bias Current Full 25 Full Offset Current 25 Full Input Resistance Common Mode Range TRANSFER CHARACTERISTICS Large Signal Voltage Gain, (VOUT = 5V, RL = 2k) Common Mode Rejection Ratio (VCM = 5.0V) Small Signal Bandwidth, (AV = 1) Channel Separation (Note 4) OUTPUT CHARACTERISTICS Output Voltage Swing (RL = 10k) (RL = 2k) Output Current, (VOUT = 5V) Full Power Bandwidth (Note 5) Output Resistance STABILITY Minimum Stable Closed Loop Gain 25 Full 25 Full Full 25 25 100 100 86 - 250 95 8 60 - 100 100 86 - 250 95 8 60 - 80 80 80 - 250 95 8 60 - kV/V kV/V dB MHz dB Full Full Full 25 25 12 10 10 16 - 13 12 15 47 110 - 12 10 10 16 - 13 12 15 47 110 - 12 10 7 16 - 13 12 15 47 110 - V V mA kHz Full 1 - - 1 - - 1 - - V/V 2 HA-5102, HA-5104 Electrical Specifications PARAMETER TRANSIENT RESPONSE (Note 6) Rise Time Overshoot Slew Rate Settling Time (Note 7) NOISE CHARACTERISTICS (Note 8) Input Noise Voltage f = 10Hz f = 1kHz Input Noise Current f = 10Hz f = 1kHz Broadband Noise Voltage f = DC to 30kHz 25 25 25 25 25 9 4.3 5.1 0.57 870 25 6.0 15 3 9 4.3 5.1 0.57 870 25 6.0 15 3 9 4.3 5.1 0.57 870 25 6.0 15 3 nV/Hz nV/Hz pA/Hz pA/Hz nVRMS 25 25 25 25 1 108 20 3 4.5 200 35 1 108 20 3 4.5 200 35 1 108 20 3 4.5 200 35 ns % V/s s VSUPPLY = 15V, Unless Otherwise Specified (Continued) TEMP. (oC) HA-5102-2 MIN TYP MAX HA-5104-2, -5 MIN TYP MAX MIN HA-5104-9 TYP MAX UNITS POWER SUPPLY CHARACTERISTICS Supply Current (All Amps) Power Supply Rejection Ratio, (VS = 5V) NOTES: 4. Channel separation value is referred to the input of the amplifier. Input test conditions are: f = 10kHz; VIN = 100mVPEAK; RS = 1k. Slew Rate 5. Full power bandwidth is guaranteed by equation: Full power bandwidth = ---------------------------- . 2V PEAK 6. Refer to Test Circuits section of the data sheet. 7. Settling time is measured to 0.1% of final value for a 10V input step, AV = -1. 8. The limits for these parameters are guaranteed based on lab characterization, and reflect lot-to-lot variation. 25 Full 86 3.0 100 5.0 86 5.0 100 6.5 80 5.0 100 6.5 mA dB 3 HA-5102, HA-5104 Test Circuits and Waveforms 2k 2k IN + 1k 50pF OUT IN + 2k 50pF OUTPUT +5V INPUT 0V -5V 200mV INPUT +5V OUTPUT 0V -5V 0V Vertical = 5V/Div., Horizontal = 5s/Div. (AV = -1) FIGURE 1. LARGE SIGNAL RESPONSE CIRCUIT Vertical = 40mV/Div., Horizontal = 50ns/Div. (AV = +1) FIGURE 2. SMALL SIGNAL RESPONSE CIRCUIT +15V 2N4416 5k 500 (NOTE 9) 5k 2k +15V + VOUT VIN 200 (NOTE 9) 2k 2k TO OSCILLOSCOPE -15V 50pF NOTES: 9. AV = -1. 10. Feedback and summing resistors should be 0.1% matched. 11. Clipping diodes are optional, HP5082-2810 recommended. FIGURE 3. SETTLING TIME CIRCUIT 4 HA-5102, HA-5104 Simplified Schematic V+ OUTPUT V+INPUT -INPUT Typical Performance Curves 15 VS = 15V, TA = 25oC HIGH 10 TYPICAL LOW 5 NOISE CURRENT (pA/Hz) 10 5.0 VS = 15V, TA = 25oC NOISE VOLTAGE (nV/Hz) 1.0 0.5 0 10 100 FREQUENCY (Hz) 1K 0.1 10 100 FREQUENCY (Hz) 1K FIGURE 4. INPUT NOISE VOLTAGE DENSITY FIGURE 5. INPUT NOISE CURRENT DENSITY 5 HA-5102, HA-5104 Typical Performance Curves (Continued) VS = 15V, TA = 25oC, 50V/Div., 1s/Div., AV = 1000V/V Input Noise = 0.232VP-P FIGURE 6. 0.1Hz TO 10Hz NOISE 2.0 INPUT OFFSET VOLTAGE (mV) VS = 15V 1.5 OFFSET VOLTAGE (mV) VS = 15V, TA = 25oC, 500V/Div., 1s/Div., AV = 1000V/V Total Output Noise = 2.075VP-P FIGURE 7. 0.1Hz TO 1MHz NOISE 2.0 TA = 25oC 1.5 1.0 1.0 0.5 0.5 0 -60 0 -40 -20 0 20 40 60 80 100 120 0 2 4 6 8 10 12 14 16 18 TEMPERATURE (oC) SUPPLY VOLTAGE (V) FIGURE 8. VIO vs TEMPERATURE FIGURE 9. VIO vs VS 4 2 VS = 15V 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 -26 -60 -40 -20 100 90 INPUT BIAS CURRENT (nA) 80 70 60 50 40 30 20 10 0 20 40 60 80 100 120 VS = 15V INPUT OFFSET CURRENT (nA) 0 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 10. IIO vs TEMPERATURE FIGURE 11. IBIAS vs TEMPERATURE 6 HA-5102, HA-5104 Typical Performance Curves 5 TOTAL SUPPLY CURRENT (mA) VS = 15V, IOUT = 0 TOTAL SUPPLY CURRENT (mA) (Continued) 5 TA = 25oC, IOUT = 0 4 4 3 3 2 2 1 1 0 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (oC) 0 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (V) FIGURE 12. ICC vs TEMPERATURE (HA-5104) FIGURE 13. ICC vs VS (HA-5102) 5 OPEN LOOP VOLTAGE GAIN (105V/V) OPEN LOOP VOLTAGE GAIN (105V/V) VS = 15V, VO = 10V, RL = 2k 5.5 5.0 VO = 10V, VS = 15V 125oC 4 25oC 4.0 3 2 3.0 -55oC 1 0 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (oC) 2.0 1K 2K 4K 6K 8K 10K LOAD RESISTANCE () FIGURE 14. AVOL vs TEMPERATURE FIGURE 15. AVOL vs LOAD RESISTANCE 290 280 270 260 250 240 230 220 210 200 190 180 170 160 150 140 130 0 TA = 25oC, RL = 2k MAX OUTPUT SWING (V) 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TA = 25oC, RL = 2k OPEN LOOP GAIN (kV/V) 2 4 6 8 10 12 14 16 18 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) FIGURE 16. AVOL vs VS FIGURE 17. VOUT vs VS 7 HA-5102, HA-5104 Typical Performance Curves 45 VS = 15V, TA = 25oC (Continued) 0 OUTPUT CURRENT (mA) 40 -20 35 CMRR (dB) 350 400 450 VOUT = -15V -40 30 VOUT = +15V 25 -60 -80 20 0 50 100 150 200 250 300 TIME (SECONDS) -100 1K 10K 100K 1M FREQUENCY (Hz) FIGURE 18. OUTPUT SHORT CIRCUIT CURRENT vs TIME FIGURE 19. CMRR vs FREQUENCY 0 POWER SUPPLY REJECTION (dB) 6 VS = 15V, RL = 2k, CL = 50pF 225 -55oC GAIN -3 -6 -40 +PSRR -PSRR -80 125oC GAIN 45 0 -60 -12 -45 125oC PHASE -55oC PHASE -135 -18 -100 1K 10K 100K 1M -24 10K 100K 1M FREQUENCY (Hz) 10M -225 40M FREQUENCY (Hz) FIGURE 20. PSRR vs FREQUENCY FIGURE 21. UNITY GAIN FREQUENCY RESPONSE 120 VOLTAGE GAIN (dB) 100 80 OVERSHOOT (%) 60 40 20 0 0 45 90 PHASE 135 100K 1M 10M 180 100M GAIN PHASE SHIFT (DEGREES) VS = 15V, TA = 25oC, RL = 2k , CL = 50pF 60 50 40 30 20 10 VS = 15V, TA = 25oC, RL = 2k 0 10 100 1K 10K LOAD CAPACITANCE (pF) 100 1K 10K FREQUENCY (Hz) FIGURE 22. OPEN LOOP GAIN vs FREQUENCY FIGURE 23. SMALL SIGNAL OVERSHOOT vs CLOAD 8 PHASE SHIFT (DEGREES) -20 VOLTAGE GAIN (dB) 0 135 HA-5102, HA-5104 Typical Performance Curves 1.1 SLEW RATE (NORMALIZED) RL = 2k, CL = 50pF, VS = 15V RISE TIME (NORMALIZED) 1.0 (Continued) 1.1 RL = 2k, CL = 50pF, VS = 15V 1.0 0.9 0.9 0.8 0.8 0.7 0.7 0.6 -60 -40 -20 0 20 40 60 80 100 120 0.6 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 24. SLEW RATE vs TEMPERATURE FIGURE 25. RISE TIME vs TEMPERATURE Die Characteristics DIE DIMENSIONS: 98.4 mils x 67.3 mils x 19 mils 2500m x 1710m x 483m METALLIZATION: Type: Al, 1% Cu Thickness: 16kA 2kA PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kA 2kA Nitride Thickness: 3.5kA 1.5kA SUBSTRATE POTENTIAL (POWERED UP): Unbiased TRANSISTOR COUNT: 93 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA-5102 V+IN1 -IN1 OUT1 +IN2 -IN2 OUT2 V+ 9 HA-5102, HA-5104 Die Characteristics DIE DIMENSIONS: 95 mils x 99 mils x 19 mils 2420m x 2530m x 483m METALLIZATION: Type: Al, 1% Cu Thickness: 16kA 2kA PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kA 2kA Nitride Thickness: 3.5kA 1.5kA SUBSTRATE POTENTIAL (POWERED UP): Unbiased TRANSISTOR COUNT: 175 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA-5104 +IN2 V+ +IN1 -IN2 -IN1 OUT2 OUT3 OUT1 OUT4 -IN3 -IN4 +IN3 V- +IN4 10 HA-5102, HA-5104 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A) 8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.405 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 10.29 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94 eA c1 D E e eA eA/2 L Q S1 e DS eA/2 c 0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 8 0.200 0.060 105o 0.015 0.030 0.010 0.0015 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 8 5.08 1.52 105o 0.38 0.76 0.25 0.038 aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH aaa bbb ccc M N 11 HA-5102, HA-5104 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.785 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 19.94 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94 eA c1 D E e eA eA/2 L Q S1 e DS eA/2 c 0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 14 0.200 0.060 105o 0.015 0.030 0.010 0.0015 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 14 5.08 1.52 105o 0.38 0.76 0.25 0.038 aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. aaa bbb ccc M N 12 HA-5102, HA-5104 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M16.3 (JEDEC MS-013-AA ISSUE C) 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 2.35 0.10 0.33 0.23 10.10 7.40 MAX 2.65 0.30 0.51 0.32 10.50 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0926 0.0040 0.013 0.0091 0.3977 0.2914 MAX 0.1043 0.0118 0.0200 0.0125 0.4133 0.2992 A1 B C D E A1 0.10(0.004) C e H h L N 0.050 BSC 0.394 0.010 0.016 16 0o 8o 0.419 0.029 0.050 1.27 BSC 10.00 0.25 0.40 16 0o 10.65 0.75 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 |
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